Linear combiners, such as digital filters, have many uses in signal processing. One of those uses is with RF sampling receivers. RF sampling receivers convert an analog RF signal directly to a digital signal, thereby eliminating RF local oscillators (LO), mixers, gain stages and filters. A wide range of applications use this type of receiver including 3G/4G base station receivers, software-defined radio (SDR) and high performance test equipment.
RF sampling typically uses an interleaved analog-to-digital converter (ADC). For example, a device may use 4 ADCs sampling alternately at 750 million samples per second (MSPS) to realize a 3 billion (giga-) samples per second (GSPS) ADC. That is, while one ADC is latching an input, the other three ADCs are processing their inputs. Thus, the four ADCs process four inputs for each period and the combined throughput is 4×750 MSPS or 3 GSPS.
However, it is difficult to perfectly match ADCs. A typical mismatch is a difference in gain and phase at different frequencies. An interleaving (IL) mismatch corrector can correct spurs caused by IL mismatches. Examples of mismatch correctors can be found in co-owned U.S. Pat. Nos. 7,916,051 and 7,915,050, which are hereby fully incorporated herein by reference. The mismatches are typically frequency dependent and need a linear corrector or filter of many coefficients or “taps.” For example, a 3 GSPS ADC using a 750MSPS ADCs typically will use a filter of 32 taps for each component ADC.
However, many applications for linear combiners, such as digital filters, must have very low power consumption. The large number of taps and the complex mathematical functions implemented by the combiners make this difficult to achieve.